Field of the Invention
The present invention relates to an information processing apparatus, a data transfer apparatus, and a control method for the data transfer apparatus and, more particularly, to power saving of the data transfer apparatus in the information processing apparatus.
Description of the Related Art
As the degree of integration of a semiconductor integration circuit increases and the processing capability improves, the power consumption increases, thereby requiring measures to reduce the power consumption.
Recent semiconductor integration circuits include a master module for generating a data transfer request, a slave module for responding to a data transfer request, and a bus system for undertaking data transfer. The master module includes a central processing unit (CPU) and a dynamic memory access controller (DMAC). The slave module includes a memory controller and a static random access memory (SRAM) module. The bus system is also called an interconnect, fabric, or on-chip network. In the master module, the power is saved by a technique called dynamic voltage and frequency scaling (DVFS) for dynamically controlling the power supply voltage and frequency, or a technique for interrupting the power supply and clock.
On the other hand, the bus system to which various master modules and slave modules are connected is often in a state in which power and a clock are always supplied in preparation for data transfer from each master module, thus it is difficult to further reduce the power consumption. When the clock frequency is switched or the power supply and clock are on/off-controlled to reduce the power consumption, transfer data may be lost or the system may freeze unless data transfer on the bus system is completed according to a specific procedure. Methods of avoiding loss of transfer data and freezing are roughly classified into a method using a software procedure and a method using a hardware mechanism.
In general, a method using a software procedure controls the power supply and clock of the bus system after confirming that no data transfer request is issued for all the master modules connected to the bus system. Also, there is proposed a method using a bus arbiter as a method using a hardware mechanism (for example, Japanese Patent No. 4733877 (literature 1)).
In recent large-scale semiconductor integration circuits, the number of master modules exceeds 100, and many master modules are driven by an external interrupt or event. In the method using a software procedure, therefore, it is difficult to ensure that all the master modules issue no data transfer requests.
Furthermore, when the power supply and clock of the bus system are controlled by the CPU, program data is speculatively loaded by a cache module and instruction fetch of the CPU, thus a special procedure is required to ensure that no data transfer is performed on the bus system. Consequently, even if it is possible to control the power supply and clock of the bus system to save the power, its opportunity is particularly limited.
In the method using the hardware mechanism described in literature 1, when currently executed processing ends, the arbiter for arbitrating a bus use right in response to assertion of a clock control request signal asserts a clock control confirmation signal by stopping assignment of the bus use right. In recent years, however, a bus system using a peer-to-peer data transfer interface is the mainstream, and an arbiter exists in the bus system. The method using the arbiter cannot interrupt the power supply of the bus system itself.